The present invention relates to a high-speed semiconductor integrated circuit and, more particularly, to an output buffer circuit used in a high-speed, large-capacity memory operating at a few hundred Mbps or more and a semiconductor memory using the same.
Recently, the operating speed and integration degree of a semiconductor memory are remarkably increasing with the advance of semiconductor technologies. The operating speed of a semiconductor memory such as a DRAM has increased to a few hundred Mbps to 1 Gbps, i.e., has become equivalent to that of a high-speed compound device, and the integration degree of a semiconductor memory has increased to a few hundred Mb or more. Accordingly, such semiconductor memories are extensively used in desktop personal computers, laptop personal computers, various servers, network-related apparatuses, PDAs, car navigation systems, game apparatuses, cell phones, and the like.
Along with this extensive use, semiconductor memories used in different applications are required to have different output characteristics, i.e., several types of output characteristics or more. Known required standards of these output characteristics are those shown in FIG. 12 (e.g., non-patent reference 1 to be described later).
FIG. 12 is a graph showing pull-down characteristic specifications of driver characteristic specifications required of an output buffer circuit of a DDR-SDRAM (Double Date Rate-Synchronous DRAM). FIG. 13 is a graph showing pull-up characteristic specifications.
As shown in FIGS. 12 and 13, the driver characteristic specifications required of the output driver disclosed in non-patent reference 1 are proposed as two types of output characteristic standards of a semiconductor memory from JEDEC in order to meet different applications. In each of FIGS. 12 and 13, a region indicated by the solid lines (i.e., a region indicated by the upper and lower limits) requires a large electric current, i.e., a small load, and is generally called full-strength. On the other hand, a region indicated by the broken lines (i.e., a region indicated by the upper and lower limits) requires a small electric current, i.e., a large load, and is generally called half-strength.
The driving current of the buffer circuit under the pull-down and pull-up half-strength conditions is substantially ½ that under the identical full-strength conditions.
Non-patent reference 1: JEDEC Solid State Technology Association 2000 “JEDEC STANDARD DDR SDRAM Specification” (Item 1112.2, Item 1112A)
As a conventional method of simultaneously satisfying the above-mentioned two types of output characteristic standards of a semiconductor memory with one type of product, the gate width of a MIS transistor forming the output buffer circuit is changed by means of, e.g., trimming, to meet the full-strength conditions and half-strength conditions. Alternatively, two types of gate masks are prepared to meet the full-strength conditions and half-strength conditions. However, these methods have problems such as addition of new steps, an increase in number of gate masks, and replacement of the gate masks.